1. Field
Exemplary embodiments of the present invention relate to a memory device and a memory system including the memory device and, more particularly, to a repair operation of a memory device and a memory system including the memory device.
2. Description of the Related Art
FIG. 1 is a block view illustrating a repair operation in a general memory device, e.g., a Dynamic Random Access Memory (DRAM) device.
A memory device may include a plurality of memory banks, an example of which is shown in FIG. 1. Referring to FIG. 1, the memory device includes a memory array 110 provided with a plurality of memory cells, a row circuit 120 for activating a word line that is selected based on a row address R_ADD, and a column circuit 130 for accessing (which means reading or writing) the data of a bit line that is selected based on a column address C_ADD.
A row fuse circuit 140 stores a repair row address REPAIR_R_ADD for a row address corresponding to a defective memory cell among the memory cells of the memory array 110. A row comparator 150 compares the repair row address REPAIR_R_ADD stored in the row fuse circuit 140 with the row address R_ADD inputted from outside of the memory device. When the repair row address REPAIR_R_ADD is the same as the row address R_ADD, the row comparator 150 performs a control on the row circuit 120 to activate a redundancy word line instead of a word line designated based on the row address R_ADD. In short, a row (which is a word line) corresponding to the repair row address REPAIR_R_ADD stored in the row fuse circuit 140 is replaced by a redundancy row (which is a redundancy word line).
A signal RACT shown in FIG. 1 is enabled in response to an active command for activating a word line in the memory array 110, and the signal RACT is disabled in response to a precharge command for deactivating a word line. Also, ‘IRD’ represents a read command, while ‘IWR’ is a write command.
The row fuse circuit 140 generally uses a laser fuse. A laser fuse stores data of a logic high level or a logic low level depending on whether the laser fuse is cut. The laser fuse may be programmed in wafer stage, but once the semiconductor wafer is put in a semiconductor package, the laser fuse cannot be programmed. Also, it is difficult to design the laser fuse below a given size due to technical limitations in decreasing its pitch length.
To alleviate such issues, as disclosed in U.S. Pat. Nos. 6,940,751, 6,777,757, 6,667,902, 7,173,851, and 7,269,047, a memory device may include a non-volatile memory such as an e-fuse array circuit, a NAND flash memory, a NOR flash memory, a Magnetoresistive Random Access Memory (MRAM), a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM), a Resistive Random Access Memory (ReRAM), a Phase-Change Random Access Memory (PC RAM) and the like, and store repair data, e.g., a repair address, in the non-volatile memory.
FIG. 2 is a block view illustrating a non-volatile memory circuit used for storing repair data in the memory device.
Referring to FIG. 2, the memory device includes a plurality of memory banks BK0 to BK3, registers 210_0 to 210_3, and a non-volatile memory circuit 201. The registers 210_0 to 210_3 are provided for the memory banks BK0 to BK3, respectively, to store repair data.
The non-volatile memory circuit 201 substitutes the row fuse circuit 140 shown in FIG. 1. The non-volatile memory circuit 201 stores repair data, for example, repair addresses, for the memory banks BK0 to BK3. The non-volatile memory circuit 201 may be one of non-volatile memories such as an e-fuse array circuit, a NAND flash memory, a NOR flash memory, a Magnetoresistive Random Access Memory (MRAM), a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM), a Resistive Random Access Memory (ReRAM), a Phase-Change Random Access Memory (PC RAM) and the like.
The registers 210_0 to 210_3 provided for the memory banks BK0 to BK3, respectively, store repair data of the corresponding memory bank. For example, the register 210_0 stores repair data of the memory bank BK0, and the register 210_2 stores repair data of the memory bank BK2. The registers 210_0 to 210_3 are formed of latch circuits, and they may store the repair data as long as power is supplied thereto. The repair data to be stored in the registers 210_0 to 210_3 are transmitted from the non-volatile memory circuit 201.
The repair data stored in the non-volatile memory circuit 201 are not directly used but moved into and stored in the registers 210_0 to 210_3 to be used. This is because the non-volatile memory circuit 201 is in an array, and it takes time to call the data stored in the array. In short, it is impossible to instantly read the data from the non-volatile memory circuit 201. This is the reason that repair operations may not be performed using data stored in the non-volatile memory circuit 201. Therefore, a boot-up operation, where the repair data stored in the non-volatile memory circuit 201 are transmitted to and stored in the registers 210_0 to 210_3, is performed. After the boot-up operation, a repair operation is performed using the data stored in the registers 210_0 to 210_3.
When the row fuse circuit 140 is substituted with the non-volatile memory circuit 201 and the registers 210_0 to 210_3, it is also possible to repair memory device defects detected after the wafer stage. Researchers and industry are further developing technology that can repair memory device defects that are detected after the fabrication of the memory device is completed and/or after the product containing the memory device is sold by accessing the non-volatile memory circuit 201.